GATE 2026 EE Q.38: solution and answer

GATE 2026 · EEQ.38 · 2 marks · MCQ

Three single-phase 11kV/3.3kV transformers are connected to form a three-phase transformer bank with connections as shown. [Figure: HV side has three single-phase transformer primary windings, one per phase, fed from lines A, B, C, each winding's dotted terminal connected directly to its own line (A, B, C respectively); a diagonal jumper connects the undotted (finish) end of the A-winding to the dotted (start) junction of the B-winding, and another diagonal jumper connects the finish of the B-winding to the start junction of the C-winding; the finish of the C-winding returns, via a bus that runs down the left side of the HV block crossing (without connecting, shown as wire hops) the B and C line taps, to the A line junction — this closes the HV windings into a delta A→B→C→A. Each HV winding is drawn on the same magnetic-core row (linked by a dashed line denoting the shared core) as one LV winding: row 1 = HV-A with LV winding for terminal a, row 2 = HV-B with LV-b, row 3 = HV-C with LV-c. On the LV side the windings are mirrored left–right: each winding's dotted terminal is on the right, tied directly to its own line (a, b, c); a diagonal jumper connects the dotted/line junction of a to the undotted (finish) end of winding b; another diagonal jumper connects the dotted/line junction of b to the finish end of winding c; the finish end of winding a is returned, via a bus running down the far-left side of the LV block (crossing, without connecting, past the b and c rows) and along the bottom, up to the dotted/line junction of c — closing the LV windings into a delta whose loop order is a→c→b→a. Both sides are labelled 'HV side' and 'LV side' respectively.] Considering ABC phase sequence, the vector group of the transformer is:

GATE 2026 EE question 38: Three single-phase transformer units drawn as three horizontal rows. — Figure from the GATE 2026 EE paper. It is part of the question.

(A)
Dd0
(B)
Dd4
(C)
Dd6
(D)
Dd10

Answer and solution

ANSWER

The correct answer is (D) Dd10.

Official answer: DSource: Official answer key, GATE 2026 EE (IIT Guwahati)

Same-core (dashed) pairs: HV-A with LV-a, HV-B with LV-b, HV-C with LV-c. Each winding's dotted end is wired directly to its own line terminal, and by the transformer dot convention the EMF phasor taken dot-to-finish on a secondary winding is in phase with the EMF phasor taken dot-to-finish on its primary partner (scaled by the real turns ratio k).
Trace the HV delta from dot to finish: A(dot)\to A(\text{finish})=B(\text{dot}), so the winding-A terminal voltage is $E_{A} = V_{A} - V_{B} = V_{A B}$ . Similarly finish of B meets dot of C, giving $E_{B} = V_{B C}$ , and finish of C returns (via the left bus) to dot of A, giving $E_{C} = V_{C A}$ .
Trace the LV delta from dot to finish. Because the LV block is drawn mirrored (dots on the right, finishes on the left), the interconnection order is reversed: finish of a meets dot of c, finish of c meets dot of b, finish of b meets dot of a — an internal loop order a\to c\to b\to a (not a\to b\to c\to a).
Writing the LV winding equations dot-to-finish: $V_{a} - V_{c} = e_{a}, V_{c} - V_{b} = e_{c}, V_{b} - V_{a} = e_{b}$ , with the same-core correspondence $e_{a} \propto E_{A} = V_{A B}$ , $e_{c} \propto E_{C} = V_{C A}$ , $e_{b} \propto E_{B} = V_{B C}$ .
With ABC phase sequence and the rotation operator $a = 1∠12 0^{\circ}$ : $V_{B C} = a^{2} V_{A B}$ and $V_{C A} = a V_{A B}$ . So, writing $k$ for the (real, positive) turns-ratio scale factor, $e_{a} = k V_{A B}, e_{c} = k a V_{A B}, e_{b} = k a^{2} V_{A B}$ .
Solve the loop with reference $V_{b} = 0$ : from $V_{b} - V_{a} = e_{b}$ , $V_{a} = - k a^{2} V_{A B}$ . (Check: $V_{c} = k a V_{A B}$ from $V_{c} - V_{b} = e_{c}$ , and then $V_{a} - V_{c} = - k a^{2} V_{A B} - k a V_{A B} = - k (a + a^{2}) V_{A B} = k V_{A B} = e_{a}$ , consistent since $1 + a + a^{2} = 0$ .)
So $V_{ab} = V_{a} - V_{b} = - k a^{2} V_{A B}$ . Since $a^{2} = 1∠ - 12 0^{\circ}$ , $- a^{2} = 1∠6 0^{\circ}$ , giving $V_{ab} = k (1∠6 0^{\circ}) V_{A B}$ — i.e. the LV line voltage $V_{ab}$ leads the HV line voltage $V_{A B}$ by $6 0^{\circ}$ .
A $6 0^{\circ}$ lead of LV over HV is the same as a $30 0^{\circ}$ lag. The clock number counts the lag of LV behind HV in $3 0^{\circ}$ steps: $30 0^{\circ} /3 0^{\circ} = 10$ .
Hence the vector group is Dd10.

KEY IDEA

For a delta-delta bank where both HV and LV windings have their dotted terminal wired straight to the line, write each winding's dot-to-finish equation from how the diagram actually interconnects it (not by assumption), use the transformer dot rule (same-core EMFs in phase, scaled by real turns ratio k) to relate LV winding phasors to the corresponding HV line phasors, then solve the delta loop KVL (with one node as reference) for the LV line-to-line phasor in terms of the HV line phasor to read off the clock number.

WATCH OUT FOR

Assuming the LV delta closes in the same left-to-right order (a\to b\to c) as it visually appears, without noticing the LV block is drawn mirrored — this silently reverses the internal loop to a\to c\to b\to a. Missing that mirroring flips the sign in the loop solution and typically leads to answering Dd0, Dd2 or Dd6 instead of the correct Dd10.

From the GATE 2026 EE paper. Every question of this paper · Download the full paper · All 14 Transformers questions, with notes

GATE 2026 EE Q.38: solution and answer

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