GATE 2026 IN Q.47: solution and answer

GATE 2026 · INQ.47 · 2 marks · MCQ

The initial state of $Q_{3} Q_{2} Q_{1} Q_{0}$ in the digital circuit shown below is 1011.

The new value of $Q_{3} Q_{2} Q_{1} Q_{0}$ after two rising edges of the clock (CLK) will be ______.

GATE 2026 IN question 47: Four positive-edge-triggered D flip-flops drawn left to right: FF3 (D_3, Q_3), FF2 (D_2, Q_2), FF1 (D_1, Q_1), FF0 (D_0… — Figure from the GATE 2026 IN paper. It is part of the question.

(A)
1101
(B)
0101
(C)
1010
(D)
1011

Answer and solution

ANSWER

After two rising edges the state goes $1011 \to 0101 \to 1010$ , so $Q_{3} Q_{2} Q_{1} Q_{0} = 1010$ . The answer is option (C).

Official answer: CSource: Official answer key, GATE 2026 IN (IIT Guwahati)

Read the next-state equations off the circuit. For a D flip-flop, $Q^{+} = D$ , so: $D_{3} = Q_{1} \oplus Q_{0}, D_{2} = Q_{3}, D_{1} = Q_{2}, D_{0} = Q_{1}$ The circuit is a right-shift register. Its serial input $D_{3}$ is the XOR of $Q_{1}$ (taken from the junction dot on the $Q_{1} \to D_{0}$ wire) and $Q_{0}$ (the feedback wire that runs back over the top).
All four flip-flops share one clock, so the circuit is synchronous. On each rising edge, every $D$ is computed from the state held before that edge, and all four outputs change together.
First rising edge, starting from $Q_{3} Q_{2} Q_{1} Q_{0} = 1011$ (so $Q_{3} = 1, Q_{2} = 0, Q_{1} = 1, Q_{0} = 1$ ): $D_{3} = 1 \oplus 1 = 0$ , $D_{2} = Q_{3} = 1$ , $D_{1} = Q_{2} = 0$ , $D_{0} = Q_{1} = 1$ . New state: $0101$ .
Second rising edge, starting from $0101$ (so $Q_{3} = 0, Q_{2} = 1, Q_{1} = 0, Q_{0} = 1$ ): $D_{3} = 0 \oplus 1 = 1$ , $D_{2} = Q_{3} = 0$ , $D_{1} = Q_{2} = 1$ , $D_{0} = Q_{1} = 0$ . New state: $1010$ .
After two rising edges, $Q_{3} Q_{2} Q_{1} Q_{0} = 1010$ . This is option (C).

KEY IDEA

In a synchronous circuit, write $Q^{+} = D$ for every flip-flop. Then work out every $D$ from the present state, update all flip-flops together on each clock edge, and repeat once per edge. Here the circuit is a right-shift register with XOR feedback: $D_{3} = Q_{1} \oplus Q_{0}$ , $D_{2} = Q_{3}$ , $D_{1} = Q_{2}$ , $D_{0} = Q_{1}$ .

WATCH OUT FOR

The most common slip is stopping after one clock edge. That gives $0101$ , which is option (B). A second mistake is updating the flip-flops one at a time, so that an already-changed $Q$ feeds the next $D$ within the same edge. A third is reading the XOR gate as an XNOR: the first edge then gives $1101$ , which is option (A). A fourth is shifting in the wrong direction. Each wire goes from $Q_{k}$ to $D_{k - 1}$ , so the bits move from $Q_{3}$ towards $Q_{0}$ .

From the GATE 2026 IN paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2026 IN Q.47: solution and answer

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