GATE 2025 IN Q.40: solution and answer

GATE 2025 · INQ.40 · 2 marks · MCQ

The clock frequency of the digital circuit shown in the figure is 12 MHz. The frequencies of the output (F) corresponding to Control = 0 and Control = 1, respectively, are

GATE 2025 IN question 40: Two positive-edge-triggered D flip-flops, FF1 (left) and FF2 (right), share one clock line labelled 'clock'… — Figure from the GATE 2025 IN paper. It is part of the question.

(A)
4 MHz and 6 MHz
(B)
6 MHz and 4 MHz
(C)
3 MHz and 4 MHz
(D)
3 MHz and 6 MHz

Answer and solution

ANSWER

(A) 4 MHz and 6 MHz. With Control = 0 the circuit is a mod-3 counter, so F = 12/3 = 4 MHz. With Control = 1, FF2 toggles on every clock edge, so F = 12/2 = 6 MHz.

Official answer: ASource: Official answer key, GATE 2025 IN (IIT Roorkee)

Read the next-state equations off the figure. Overline means complement, and $C$ stands for Control. $D_{1} = \overline{Q_{2}}$ , $D_{2} = \overline{Q_{2}} (Q_{1} + C)$ , and the output is $F = \overline{Q_{2}}$ . Both flip-flops share the clock, and for a D flip-flop $Q^{+} = D$ .
Control = 1: $Q_{1} + 1 = 1$ , so $D_{2} = \overline{Q_{2}}$ . FF2 is wired as a toggle flip-flop and changes state on every clock edge, whatever $Q_{1}$ is.
A toggling output completes one full cycle every 2 clock periods, so it divides the clock by 2: $f_{F} = \frac{12 MHz}{2} = 6 MHz$ .
Control = 0: $D_{2} = \overline{Q_{2}} Q_{1}$ and $D_{1} = \overline{Q_{2}}$ . Trace the states $(Q_{1} Q_{2})$ with $Q^{+} = D$ . From $00$ : $D_{1} = 1$ , $D_{2} = 1 \cdot 0 = 0$ , so the next state is $10$ . From $10$ : $D_{1} = 1$ , $D_{2} = 1 \cdot 1 = 1$ , so the next state is $11$ . From $11$ : $\overline{Q_{2}} = 0$ makes both D inputs 0, so the next state is $00$ .
The unused state $01$ also has $\overline{Q_{2}} = 0$ , so $D_{1} = D_{2} = 0$ and it goes to $00$ . Whatever state the circuit starts in, it ends up in the 3-state cycle $00 \to 10 \to 11 \to 00$ .
Over one cycle $F = \overline{Q_{2}}$ reads $1, 1, 0$ , so it repeats every 3 clock periods (duty cycle $\frac{2}{3}$ ): $f_{F} = \frac{12 MHz}{3} = 4 MHz$ .
So F is 4 MHz for Control = 0 and 6 MHz for Control = 1, which is option (A).

KEY IDEA

Write the D-input equations and trace the state sequence. The output frequency is the clock frequency divided by the number of clock periods before F repeats. With Control = 1 the OR gate is forced to 1 and FF2 becomes a toggle flip-flop (divide by 2). With Control = 0 the feedback from $\overline{Q_{2}}$ gives the 3-state cycle 00 -> 10 -> 11 (divide by 3). The unused state 01 falls into that cycle.

WATCH OUT FOR

Assuming two flip-flops always make a mod-4 counter and dividing by 4 (3 MHz, options C and D), without tracing the states. Another is swapping the order the question asks for (Control = 0 first), which gives option (B).

From the GATE 2025 IN paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

GATE 2025 IN Q.40: solution and answer

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