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GATE 2024 EC Q.42: solution and answer

GATE 2024 · ECQ.42 · 2 marks · MCQ

The sequence of states of the given synchronous sequential circuit is ________.

GATE 2024 EC question 42: Two positive-edge-triggered T flip-flops share a common clock line CLK (the clock inputs are drawn with a triangle and no…Tap to open full size
Figure from the GATE 2024 EC paper. It is part of the question.
Figure description

Two positive-edge-triggered T flip-flops share a common clock line CLK (the clock inputs are drawn with a triangle and no bubble). Flip-flop 1 (left) has input T_1 and outputs Q_1 and Q_1; Q_1 is not connected to anything. Flip-flop 0 (right) has input T_0 and outputs Q_0 and Q_0. OR gate 1 drives T_1. Its top input is fed back from Q_1: a wire leaves the junction dot on the Q_1 output, goes up, runs left and comes down into the gate. Its bottom input is Q_0: a wire leaves Q_0, goes right, down, left along the bottom of the drawing and up into the gate. So T_1 = Q_1 + Q_0. OR gate 2 drives T_0. One input is Q_1, taken straight from the junction dot. The other is Q_0, fed back through a wire that goes right from Q_0, up, left along the top and down into the gate. So T_0 = Q_1 + Q_0. There are no external inputs other than CLK.

  1. (A)

    00 → 10 → 11 → 00

  2. (B)

    11 → 00 → 10 → 01 → 00

  3. (C)

    01 → 10 → 11 → 00 → 01

  4. (D)

    00 → 01 → 10 → 00

Answer and solution

ANSWER

The state sequence is , so the answer is option (B).

Official answer: BSource: Official answer key, GATE 2024 EC (IISc Bengaluru)

  1. Read the flip-flop inputs off the wiring. Complement is written with \overline{} (no prime is used). OR gate 1 takes (fed back from the junction dot) and (the wire along the bottom of the drawing). OR gate 2 takes (from the same dot) and (the wire along the top). So

  2. Use the T flip-flop characteristic equation . The flip-flop toggles when and holds when .

  3. State : , so toggles to 1. , so holds at 0. Next state: .

  4. State : , so toggles to 0. , so toggles to 1. Next state: .

  5. State : , so holds at 0. , so toggles to 0. Next state: .

  6. State : and , so both flip-flops toggle. Next state: .

  7. Putting it together: . The circuit cycles through , and state drops into that cycle at . This is option (B). Options (A) and (C) both send to (and (C) also sends to ), and (D) sends to . None of these transitions is what the circuit does.

KEY IDEA

Trace the wiring to get the excitation equations and . Then use to find the next state for all four present states. Because feeds both OR gates, both flip-flops toggle whenever . That fact alone gives and .

WATCH OUT FOR

Treating the T input as if it were a D input () instead of a toggle (). Doing that gives , the wrong transition in options (A) and (C). A second common slip is misreading the long feedback wires: taking into gate 1 instead of , or missing the feedback into gate 1. Students also often skip state . It is outside the main cycle, but option (B) starts from it, so you have to check it.

From the GATE 2024 EC paper. Every question of this paper · Download the full paper · All 30 Sequential questions, with notes

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