GATE 2018 IN Q.45: solution and answer

GATE 2018 · INQ.45 · 2 marks · NAT

A portion of an assembly language program written for an 8-bit microprocessor is given below along with explanations. The code is intended to introduce a software time delay. The processor is driven by a 5 MHz clock. The time delay (in $μ$ s) introduced by the program is ________.

        MVI B, 64H   ; Move immediate the given byte into register B. Takes 7 clock periods.
LOOP :  DCR B        ; Decrement register B. Affects Flags. Takes 4 clock periods.
        JNZ LOOP     ; Jump to address with Label LOOP if zero flag is not set. Takes
                     ; 10 clock periods when jump is performed and 7 clock periods when
                     ; jump is not performed.

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Answer and solution

ANSWER

The program introduces a delay of $1404 \times 0.2 μ s = 280.8 μ s$ .

Official answer: 279 to 282Source: Official answer key, GATE 2018 IN (IIT Guwahati)

Convert the loop count to decimal: $(64)_{16} = 6 \times 16 + 4 = (100)_{10}$ . So $B$ starts at 100, and the loop body DCR B runs 100 times, once for each value from 100 down to 1.
JNZ LOOP jumps whenever $B \neq = 0$ after the decrement. That happens 99 times, after $B$ becomes $99, 98, \dots, 1$ . On the 100th pass $B$ becomes 0, the zero flag is set ( $Z = 1$ ), and the jump is not taken. This happens once.
Count the clock periods (T-states) for each instruction: $MVI B, 64H DCR B JNZ (taken) JNZ (not taken) : 1 \times 7 = 7 : 100 \times 4 = 400 : 99 \times 10 = 990 : 1 \times 7 = 7$
Total: $N_{T} = 7 + 400 + 990 + 7 = 1404$ clock periods.
Clock period: $T = \frac{1}{f} = \frac{1}{5 MHz} = 0.2 μ s$ . The question says each count is in clock periods of the 5 MHz clock that drives the processor.
Delay: $t_{d} = N_{T} \times T = 1404 \times 0.2 μ s = 280.8 μ s$ .

KEY IDEA

For a delay loop with an initial count $N$ , the loop body runs $N$ times, but the conditional jump is taken only $N - 1$ times and falls through once, at its shorter not-taken time. The total T-states are $N_{T} = T_{init} + N T_{DCR} + (N - 1) T_{JNZ,taken} + T_{JNZ,not taken}$ , and the delay is $N_{T} / f$ . Convert a hexadecimal count such as $64 H$ to decimal first.

WATCH OUT FOR

Reading $64 H$ as decimal 64 gives $7 + 256 + 630 + 7 = 900$ T-states, or $180 μ s$ . Another error is to halve the 5 MHz clock, as if it were an 8085 crystal frequency, which doubles the answer to $561.6 μ s$ . The question states that the processor itself is driven by a 5 MHz clock, so $T = 0.2 μ s$ . Counting the jump as taken all 100 times is also wrong, even though it happens to land inside the key's range here.

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GATE 2018 IN Q.45: solution and answer

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