GATE 2025 IN Q.42: solution and answer

GATE 2025 · INQ.42 · 2 marks · MCQ

An 8-bit microprocessor has 16-bit address bus ( $A_{15} - A_{0}$ ) where $A_{0}$ is the LSB. As shown in Figure (a), it has a pre-installed 4 KB ROM whose starting address is 0000 H. The processor needs to be upgraded by adding a 16 KB RAM as shown in Figure (b). The address range for the newly added RAM is

GATE 2025 IN question 42: Figure (a), labelled 'Pre-installed ROM': a block marked '4 KB ROM' inside a dotted box. — Figure from the GATE 2025 IN paper. It is part of the question.

(A)
1000 H – 4FFF H
(B)
3000 H – 6FFF H
(C)
4000 H – 7FFF H
(D)
8000 H – BFFF H

Answer and solution

ANSWER

The newly added 16 KB RAM occupies 4000 H to 7FFF H, which is option (C).

Official answer: CSource: Official answer key, GATE 2025 IN (IIT Roorkee)

Size check: $16 KB = 16 \times 1024 = 2^{14}$ locations, so the RAM uses the 14 address lines $A_{13} \dots A_{0}$ internally. The remaining lines $A_{15}$ and $A_{14}$ go to the chip-select logic.
Decoding logic (the prime means complement): $A_{14}$ passes through the inverter and $A_{15}$ goes straight into the OR gate, so the RAM's chip select is $\overline{C S} = A_{15} + A_{14}^{'}$ .
$\overline{C S}$ is active low, so the RAM is selected only when $A_{15} + A_{14}^{'} = 0$ . An OR output is 0 only if every input is 0. So $A_{15} = 0$ and $A_{14}^{'} = 0$ , which means $A_{14} = 1$ .
Lowest address: $A_{15} A_{14} = 01$ with $A_{13} \dots A_{0}$ all 0, which is $(0100000000000000)_{2} = 4000 H$ .
Highest address: $A_{15} A_{14} = 01$ with $A_{13} \dots A_{0}$ all 1, which is $(0111111111111111)_{2} = 7FFF H$ .
Consistency check: the ROM's $\overline{C S} = A_{12} + A_{13} + A_{14} + A_{15}$ is 0 only when all four lines are 0, so the ROM occupies $0000 H$ to $0FFF H$ ( $2^{12}$ locations $= 4 KB$ , starting at $0000 H$ as the question says). This does not overlap $4000 H$ to $7FFF H$ . The RAM spans $(7 FFF)_{16} - (4000)_{16} + 1 = (4000)_{16} = 16384$ locations $= 16 KB$ , which matches its size.
So the RAM's address range is $4000 H$ to $7FFF H$ , which is option (C).

KEY IDEA

Address lines that go straight into a memory chip change freely across its range. The lines that feed the chip-select logic are fixed at the values that make the active-low $\overline{C S}$ equal to 0. Here $\overline{C S} = A_{15} + A_{14}^{'}$ is 0 only for $A_{15} A_{14} = 01$ . The 14 free lines $A_{13} \dots A_{0}$ then run from all 0s to all 1s, giving $4000 H$ to $7FFF H$ .

WATCH OUT FOR

Treating $\overline{C S}$ as active high, or forgetting the inverter on $A_{14}$ . Both errors give $A_{15} A_{14} = 00$ or $10$ , which lands on a wrong block such as $8000 H$ to $BFFF H$ (option D). Another trap is placing the RAM straight after the 4 KB ROM at $1000 H$ (option A). The decoder, not the ROM's size, decides where the RAM sits, and a 16 KB block decoded on $A_{15} A_{14}$ always starts on a 16 KB boundary.

From the GATE 2025 IN paper. Every question of this paper · Download the full paper · All 9 Processors & memory questions, with notes

GATE 2025 IN Q.42: solution and answer

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