GATE 2018 EC Q.32: solution and answer

GATE 2018 · ECQ.32 · 2 marks · MCQ

A $2 \times 2$ ROM array is built with the help of diodes as shown in the circuit below. Here W0 and W1 are signals that select the word lines and B0 and B1 are signals that are output of the sense amps based on the stored data corresponding to the bit lines during the read operation.

[Figure: diode ROM array; beside it the matrix of bits stored in the ROM array, rows $W_{0}, W_{1}$ , columns $B_{0}, B_{1}$ : $[D_{00} D_{10} D_{01} D_{11}]$ ]

During the read operation, the selected word line goes high and the other word line is in a high impedance state. As per the implementation shown in the circuit diagram above, what are the bits corresponding to $D_{ij}$ (where $i = 0$ or $1$ and $j = 0$ or $1$ ) stored in the ROM?

GATE 2018 EC question 32: Two horizontal word lines, W0 (top) and W1 (below it), cross two vertical bit lines, B0 (left) and B1 (right). — Figure from the GATE 2018 EC paper. It is part of the question.

(A)
$[1001]$
(B)
$[0110]$
(C)
$[1100]$
(D)
$[1010]$

Answer and solution

ANSWER

The ROM stores $[D_{00} D_{10} D_{01} D_{11}] = [1001]$ , which is option (A).

Official answer: ASource: Official answer key, GATE 2018 EC (IIT Guwahati)

Bit-line default. Each bit line ends in a MOSFET whose source is grounded and whose gate is tied to $V_{D D}$ . The symbol has no gate bubble, so it is n-channel, and it is always on. It acts as a pull-down load: if nothing drives a bit line high, the sense amp reads it as $0$ .
Diode orientation. Both diodes have the anode on a word line and the cathode on a bit line. A diode conducts only when its word line is high. It then pulls that bit line up to about one diode drop below the word-line high level, roughly $V_{D D} - V_{γ}$ , which the sense amp reads as $1$ . So a diode at a crossing stores a $1$ and a crossing with no diode stores a $0$ .
Unselected line. The unselected word line is in a high-impedance state, so it cannot drive any bit line high or low. The diodes conduct only from a word line to a bit line, never back. Each bit line also has only one diode on it, so there is no sneak path through the other row, and only the selected row sets the outputs.
Read row $W_{0}$ ( $W_{0}$ high). The diode from $W_{0}$ to $B_{0}$ conducts, so $B_{0} = 1$ . There is no diode at the $W_{0}$ – $B_{1}$ crossing, so the always-on MOSFET holds $B_{1}$ low and $B_{1} = 0$ . This gives $D_{00} = 1$ and $D_{01} = 0$ .
Read row $W_{1}$ ( $W_{1}$ high). The diode from $W_{1}$ to $B_{1}$ conducts, so $B_{1} = 1$ . There is no diode at the $W_{1}$ – $B_{0}$ crossing, and the diode on $B_{0}$ has its anode on the floating line $W_{0}$ , so it cannot conduct. The MOSFET holds $B_{0}$ low and $B_{0} = 0$ . This gives $D_{10} = 0$ and $D_{11} = 1$ .
Stored matrix: $[D_{00} D_{10} D_{01} D_{11}] = [1001]$ This is option (A).

KEY IDEA

In a diode ROM, the always-on transistor at the foot of each bit line pulls it low by default. A diode from a word line (anode) to a bit line (cathode) pulls that bit line high when the row is selected. So a diode at a crossing stores $1$ and an empty crossing stores $0$ . Read the matrix straight off the diode positions: row $W_{0}$ has a diode only on $B_{0}$ and row $W_{1}$ only on $B_{1}$ .

WATCH OUT FOR

Treating a diode as a stored $0$ , as if it pulled the line low, which gives option (B). Here the default level comes from the pull-down transistor with its gate tied to $V_{D D}$ , so a diode drives the line high and marks a $1$ . A second slip is reading the matrix by column instead of by row, or taking the diode's anode position (the $W_{1}$ diode's anode sits between $B_{0}$ and $B_{1}$ ) as its column. The column is set by the bit line the cathode lands on.

From the GATE 2018 EC paper. Every question of this paper · Download the full paper · All 9 Processors & memory questions, with notes

GATE 2018 EC Q.32: solution and answer

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