IAE Academy

GATE 2025 CS1 Q.27: solution and answer

GATE 2025 · CS1Q.27 · 1 mark · MSQ

A partial data path of a processor is given in the figure, where RA, RB, and RZ are 32-bit registers. Which option(s) is/are CORRECT related to arithmetic operations using the data path as shown?

GATE 2025 CS1 question 27: A data path diagram.Tap to open full size
Figure from the GATE 2025 CS1 paper. It is part of the question.
Figure description

A data path diagram. Two input registers feed two 2:1 multiplexers: RA (32 bit) feeds down into Mux_A; RB (32 bit) feeds down into Mux_B. Mux_A also receives a second input labeled "immediate value, 32 bit" from the left, with a select line labeled "Select RA/immediate" feeding into Mux_A. Mux_B also receives a second input labeled "immediate value, 32 bit" from the right, with a select line labeled "Select RB/immediate" feeding into Mux_B. The outputs of Mux_A and Mux_B (each 32 bit, marked with slash-32 tick marks) both feed down into a single ALU block (drawn as a trapezoid). The ALU also receives multiple "ALU control" input lines from the left (drawn as a bus of several arrows). The ALU's output (32 bit) feeds down into register RZ (32 bit).

  1. (A)

    The data path can implement arithmetic operations involving two registers.

  2. (B)

    The data path can implement arithmetic operations involving one register and one immediate value.

  3. (C)

    The data path can implement arithmetic operations involving two immediate values.

  4. (D)

    The data path can only implement arithmetic operations involving one register and one immediate value.

Answer and solution

ANSWER

The correct options are (A), (B) and (C).

Official answer: A, B, CSource: Official answer key, GATE 2025 CS1 (IIT Roorkee)

  1. Mux_A is a 2:1 multiplexer whose inputs are RA and a 32-bit immediate value; it is controlled by its own dedicated select line labeled "Select RA/immediate".

  2. Mux_B is a 2:1 multiplexer whose inputs are RB and a 32-bit immediate value; it is controlled by its own dedicated select line labeled "Select RB/immediate".

  3. Because these two select lines are physically separate signals in the figure (not a single shared control), they can be set independently, so all 2×2 = 4 combinations of (Mux_A output, Mux_B output) are realizable at the ALU's two 32-bit operand inputs.

  4. Combination (RA, RB): both muxes select their register input → the ALU operates on two registers → option (A) is correct.

  5. Combination (RA, immediate) or (immediate, RB): one mux selects its register, the other selects its immediate input → the ALU operates on one register and one immediate value → option (B) is correct.

  6. Combination (immediate, immediate): both muxes select their immediate input → the ALU operates on two immediate values → option (C) is correct.

  7. Since two-register operation (A) and two-immediate operation (C) are both achievable, the data path is not restricted to only "one register and one immediate value" operations, so option (D)'s exclusive claim is false.

  8. Final answer: options (A), (B) and (C) are correct.

KEY IDEA

Mux_A and Mux_B are controlled by two separate, independent select lines ("Select RA/immediate" and "Select RB/immediate"), so all four combinations of their inputs (RA/RB, RA/immediate, immediate/RB, immediate/immediate) are physically realizable at the ALU's two operand ports.

WATCH OUT FOR

Assuming the two multiplexer select lines must be tied together (i.e., both muxes always pick "register" or both always pick "immediate" in lock-step), which would wrongly eliminate option (C) and make (D) look correct. The figure shows two independent select lines ("Select RA/immediate" and "Select RB/immediate"), so each mux can be controlled separately.

From the GATE 2025 CS1 paper. Every question of this paper · Download the full paper · All 5 ALU & control unit questions, with notes

More ALU & control unit questions