GATE 2023 EE Q.44: solution and answer

GATE 2023 · EEQ.44 · 2 marks · MSQ

All the elements in the circuit shown in the following figure are ideal. Which of the following statements is/are true?

GATE 2023 EE question 44: A common bottom rail (ground) joins the negative terminals of three DC voltage sources and the lower contact of a switch. — Figure from the GATE 2023 EE paper. It is part of the question.

(A)
When switch S is ON, both D1 and D2 conducts and D3 is reverse biased
(B)
When switch S is ON, D1 conducts and both D2 and D3 are reverse biased
(C)
When switch S is OFF, D1 is reverse biased and both D2 and D3 conduct
(D)
When switch S is OFF, D1 conducts, D2 is reverse biased and D3 conducts

Answer and solution

ANSWER

(B) and (C) are true. With S ON, node R sits at 0 V, so D1 conducts and D2 and D3 are reverse biased. With S OFF, the 2 A source forces current through D3, which puts node R at 40 V. D2 then conducts, and D1 is reverse biased.

Official answer: B, CSource: Official answer key, GATE 2023 EE (IIT Kanpur)

Take the bottom rail as $0 V$ and name the nodes. P is where the 4 A source, D1 and D2 meet. Q is the top of the 20 V source, so $V_{Q} = 20 V$ . R is where D1, the 2 A source, S and D3 meet. D3's cathode is held at $40 V$ . For an ideal diode, ON means $V_{A K} = 0$ with forward current $\geq 0$ , and OFF means $V_{A K} \leq 0$ with zero current. An ideal current source can sit at any voltage, so the 4 A source always pushes $4 A$ into P. The 10 V source is in series with it, so it does not fix $V_{P}$ .
S ON: the closed switch makes $V_{R} = 0 V$ . D3 then has $V_{A K} = 0 - 40 = - 40 V$ , so D3 is reverse biased.
By KCL at node P, the forced $4 A$ has to leave through D1 or D2. Suppose D2 conducts. Then $V_{P} = V_{Q} = 20 V$ , which would put $V_{A K} = 20 - 0 = + 20 V$ across D1. An ideal diode cannot have a positive $V_{A K}$ , so D2 cannot conduct.
So D1 carries the whole $4 A$ , and $V_{P} = V_{R} = 0 V$ . D2 then has $V_{A K} = 0 - 20 = - 20 V$ , so it is reverse biased. Check at node R: $4 + 2 = 6 A$ flows down through S, and nothing breaks. Statement (B) is true. Statement (A) is false because D2 does not conduct.
S OFF: with S open, D3 is the only way out of node R. KCL there gives $I_{D 3} = I_{D 1} + 2 A$ . Since $I_{D 1} \geq 0$ , $I_{D 3} \geq 2 A > 0$ . So D3 must conduct, and $V_{R} = 40 V$ .
Now node P. If D1 conducted, $V_{P} = V_{R} = 40 V$ , and D2 would see $V_{A K} = 40 - 20 = + 20 V$ . That is impossible, so D1 does not conduct. The 4 A must go somewhere, so D2 conducts: $V_{P} = 20 V$ and $I_{D 2} = 4 A$ . D1 then has $V_{A K} = 20 - 40 = - 20 V$ , so it is reverse biased.
Check: $I_{D 1} = 0$ , so $I_{D 3} = 0 + 2 = 2 A > 0$ , which agrees with step 5. At node Q, $4 A$ comes in through D2 and $2 A$ leaves through the 2 A source, so $2 A$ goes into the $+$ terminal of the 20 V source. An ideal source accepts that. The ideal current sources take up whatever voltage is left: the 4 A source sits between $10 V$ and $20 V$ , and the 2 A source between $20 V$ and $40 V$ . Statement (C) is true. Statement (D) is false because D1 is reverse biased.
Correct options: (B) and (C).

KEY IDEA

An ideal current source pushes its current whatever the voltage across it. So KCL at a node fed by a current source forces at least one diode leaving that node to conduct. Once you know which diode must carry the current, use the ideal-diode rule (a conducting diode has $V_{A K} = 0$ , and no diode can have $V_{A K} > 0$ ) to decide which of the rival diodes is the one.

WATCH OUT FOR

Taking the 10 V source as the voltage of node P. It is in series with the 4 A source, so it fixes neither $V_{P}$ nor the current. The second common slip is assuming D3 can be off when S is OFF. With the switch open, the 2 A source's current into node R has no other way out, so D3 must conduct and clamp R at 40 V.

From the GATE 2023 EE paper. Every question of this paper · Download the full paper · All 25 Diode circuits questions, with notes

GATE 2023 EE Q.44: solution and answer

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