ISRO EC 2025 Q.76: solution and answer

Official answer: CSource: ISRO's final answer key of 15 May 2026

1. A memory of size $M\times N$ has $M$ locations (words) of $N$ bits each. Each chip is $4\times 4$: $4$ locations of $4$ bits, so it needs ${\log }_{2}4=2$ address lines.

2. With all address buses tied together, every chip receives the same $2$-bit address and responds to every access. The number of locations therefore does not grow: it stays at $4$.

3. Each chip supplies its own $4$ data lines, and these sit side by side as separate bits of the same word. This is word-size expansion: $4\times 4=16$ bits per word.

4. Total capacity is $4\times 16=64$ bits, which equals four chips of $16$ bits each, as it must.

5. The system is $4\times 16$ ($4$ words of $16$ bits), which is option (c).

6. Why the others fail: $16\times 4$ is $16$ locations of $4$ bits. It would need depth expansion, with the chips holding different address ranges and a decoder on two extra address lines, not a shared address bus. $256\times 4$ ($1024$ bits) and $8\times 4$ ($32$ bits) do not match the $64$-bit total.