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GATE 2026 CS1 Q.16: solution and answer

GATE 2026 · CS1Q.16 · 1 mark · MCQ

Which one of the following dependencies among the register operands of different instructions can cause a data hazard in a pipelined processor?

  1. (A)

    Read-after-read

  2. (B)

    Read-after-write

  3. (C)

    Write-after-read

  4. (D)

    Write-after-write

See the question in the paper

Answer and solution

ANSWER

The correct answer is (B) Read-after-write.

Official answer: BSource: Official answer key, GATE 2026 CS1 (IIT Guwahati)

  1. A data hazard occurs when overlapping (pipelined) execution of instructions can change the outcome relative to strictly sequential execution, due to a dependency through a shared register operand.

  2. Read-after-read (RAR): both instructions only read the register. Reads don't change the register's value, so the order in which they read it doesn't matter — no hazard.

  3. Write-after-read (WAR) and write-after-write (WAW): in a simple single-issue, in-order pipeline, every instruction reads its operands (ID stage) and writes its result (WB stage) strictly in program order, so a later instruction can never overtake an earlier one's read or write. WAR/WAW can only cause trouble under out-of-order or overlapped-write execution, not in this standard in-order pipeline — so they are not the answer here.

  4. Read-after-write (RAW): a later instruction needs to read a register that an earlier instruction has not yet finished computing/writing. If the read (in ID) happens before the earlier instruction's write (in WB) has completed, the pipeline reads a stale value — producing a wrong result unless stalled or the value is forwarded. This is a genuine data hazard even in a simple in-order pipeline.

  5. Since RAW is the only one of the four dependencies that can actually corrupt a result under ordinary in-order pipelined execution, it is the dependency that causes a data hazard.

  6. Hence the answer is Read-after-write, option (B).

KEY IDEA

In a simple in-order pipeline, only a true (flow) dependency — a later instruction reading a register before an earlier instruction has finished writing it — can produce an incorrect result; this is the Read-After-Write (RAW) hazard.

WATCH OUT FOR

Confusing RAW (a true data dependency that causes a real hazard even in a simple in-order pipeline) with WAR/WAW (anti- and output-dependencies, which only matter under out-of-order or overlapped-write execution) — or picking RAR by mistakenly treating any repeated access as hazardous.

From the GATE 2026 CS1 paper. Every question of this paper · Download the full paper · All 12 Pipelining questions, with notes

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