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GATE 2024 CS1 Q.30: solution and answer

GATE 2024 · CS1Q.30 · 1 mark · MSQ

Consider a 5-stage pipelined processor with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Register Writeback (WB) stages. Which of the following statements about forwarding is/are CORRECT?

  1. (A)

    In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction

  2. (B)

    In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction

  3. (C)

    Forwarding cannot prevent all pipeline stalls

  4. (D)

    Forwarding does not require any extra hardware to retrieve the data from the pipeline stages

See the question in the paper
GATE 2024 CS1 question 30Tap to open full size

Answer and solution

ANSWER

The correct answer is A, B, C — all three statements about forwarding are correct, while D is false because forwarding requires extra hardware (bypass paths, multiplexers, and forwarding-unit control logic).

Official answer: A, B, CSource: Official answer key, GATE 2024 CS1 (IISc Bengaluru)

  1. Definition check (A): Forwarding means a result computed at a source stage of an earlier instruction is passed directly to the destination stage of a later instruction that needs it, without waiting for it to be written back to the register file. This is the standard definition, so (A) is correct.

  2. Check (B): The MEM/WB pipeline latch holds the output of the MEM stage. This value can be forwarded to the EX stage input (e.g., an ALU operand) of a following instruction — this is the classic MEM/WB → EX forwarding path used in a 5-stage pipeline. So (B) is correct.

  3. Check (C): Even with full EX/MEM and MEM/WB forwarding in place, a load-use hazard (the instruction right after a load needs the loaded value in its own EX stage, before the load has produced it) cannot be resolved by forwarding — the pipeline must still insert at least one stall cycle. So forwarding reduces stalls but does not prevent all of them, making (C) correct.

  4. Check (D): Forwarding needs dedicated bypass datapaths from stage-output latches to stage inputs, multiplexers to select between the forwarded value and the normal register-file value, and forwarding-unit control logic to detect hazards and drive those multiplexers. This is genuine extra hardware, so the claim of 'no extra hardware' is false, making (D) incorrect.

  5. Since this is an MSQ, the correct set is every true statement: A, B, and C.

KEY IDEA

Forwarding (bypassing) routes a computed result directly from the pipeline stage that produces it to the pipeline stage that needs it, bypassing the register file/writeback, but it needs dedicated bypass wires, multiplexers, and forwarding-unit control logic, and it still cannot eliminate a load-use hazard (where the needed value does not exist yet when the dependent instruction reaches EX).

WATCH OUT FOR

Assuming forwarding is a "free" software-level trick with no hardware cost (missing why D is false), or assuming forwarding alone eliminates every stall and forgetting the load-use hazard, which still forces at least one bubble even with full forwarding (which is why C is true, not false).

From the GATE 2024 CS1 paper. Every question of this paper · Download the full paper · All 12 Pipelining questions, with notes

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