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GATE 2025 CS1 Q.11: solution and answer

GATE 2025 · CS1Q.11 · 1 mark · MCQ

Suppose a program is running on a non-pipelined single processor computer system. The computer is connected to an external device that can interrupt the processor asynchronously. The processor needs to execute the interrupt service routine (ISR) to serve this interrupt. The following steps (not necessarily in order) are taken by the processor when the interrupt arrives:

(i) The processor saves the content of the program counter.
(ii) The program counter is loaded with the start address of the ISR.
(iii) The processor finishes the present instruction.

Which ONE of the following is the CORRECT sequence of steps?

  1. (A)

    (iii), (i), (ii)

  2. (B)

    (i), (iii), (ii)

  3. (C)

    (i), (ii), (iii)

  4. (D)

    (iii), (ii), (i)

See the question in the paper
GATE 2025 CS1 question 11Tap to open full size

Answer and solution

ANSWER

The correct sequence is (iii) → (i) → (ii): finish the current instruction, save the program counter, then load the PC with the ISR's start address — option A.

Official answer: ASource: Official answer key, GATE 2025 CS1 (IIT Roorkee)

  1. Interrupts in a non-pipelined processor are recognized only at instruction boundaries, so the processor must first complete the instruction currently executing: step (iii) happens first.

  2. Before the program counter can be reused, the return address it holds must be preserved so execution can resume later: the processor saves the program counter, step (i), immediately after finishing the instruction.

  3. Only after the PC is safely saved can it be overwritten: it is loaded with the ISR's start address, step (ii), transferring control to the interrupt service routine.

  4. This gives the unique valid order (iii) → (i) → (ii), which is option A.

KEY IDEA

Interrupt handling in a non-pipelined processor follows a fixed order dictated by hardware necessity: interrupts are checked and honored only at instruction boundaries, and the return address (PC) must be preserved before it is overwritten with the ISR's address.

WATCH OUT FOR

Assuming the PC is loaded with the ISR address before or without first saving it, or forgetting that a non-pipelined processor only recognizes interrupts at instruction boundaries (so the current instruction must finish first).

From the GATE 2025 CS1 paper. Every question of this paper · Download the full paper · All 8 I/O, interrupts & DMA questions, with notes

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